As an example of a semiconductor integrated circuit comprising a MOSFET with two kinds of gate oxide film thicknesses, U.S. Pat. No. 6,380,764 (JP-A 195976/1999) was reported. According to said patent document, in a semiconductor integrated circuit having a plurality of signal paths, in the case of a path having a margin for delay of signal propagation along the signal path, the device consists of a MOSFET with a high threshold voltage. On the other hand, in the case of a path having no margin for delay, the device consists of a MOSFET with a low threshold voltage which has a large sub-threshold leakage voltage, but faster operation speed.
A means of realizing the above-described high threshold voltage and low threshold voltage MOSFETs is selected from the following: changing the impurity content of the semiconductor substrate underneath the gate oxide film, changing the thickness of the gate oxide film, changing the substrate bias voltage applied to the well region, changing the gate length, and a combination of these techniques.
The present inventors investigated an element routing method suitable for high integration with a simplified manufacturing process for CMOS circuits when the CMOS circuits consist of a MOSFET with the above-described two kinds of gate oxide film thickness. In contrast to the present invention, the prior art technique described in said patent document focuses on increasing speed and lowering power consumption of the semiconductor integrated circuit device and does not concern itself with high integration and simplifying the manufacturing process of CMOS circuits using MOSFETs with two kinds of gate oxide film thickness.